Existing programmable memories consist mostly of field effect transistors with thick floating gate dielectric layers to enable charge storage. The floating gate dielectric layer must be of sufficient thickness, typically greater than 8 nm, to avoid loss of stored charge through the tunneling process. As technology advances, the requirement of thick floating gate dielectric layer may not be compatible with CMOS logic transistor processes because advanced CMOS logic transistors employ relatively thin gate dielectric layers, typically less than 3 nm, for use as floating gate dielectric.